I am a newbie to Verilog and had a problem while defining a if-else loop. The error message is
A net is not a legal lvalue in this context" for all assign statements in the given code.
always @(adbar) if (adbar==1'b1) begin assign Z[0] = m_out[0]; assign Z[1] = m_out[1]; assign Z[2] = m_out[2]; assign Z[3] = X[5]; assign Z[4] = X[6]; assign Z[5] = X[7]; assign Z[6] = m_out[3]; assign Z[7] = m_out[4]; end else begin assign Z[0] = m_out[0]; assign Z[1] = m_out[1]; assign Z[2] = m_out[2]; assign Z[3] = X[3]; assign Z[4] = X[4]; assign Z[5] = X[5]; assign Z[6] = m_out[3]; assign Z[7] = m_out[4]; end endmodule The full program is given below. All the modules have been properly defined and I am sure that the error is only in this part.
module my_decoder (X,adbar, clear, clock, Z); input [7:0] X; input adbar; input clear, clock; output [7:0] Z; wire clear, clock; wire [7:0] Z; wire [4:0] d_out; wire [4:0] x_out; wire [4:0] m_out; wire [4:0] n_out; wire sel1; wire c_out1; wire c_out2; wire c_out3; mux2_gate_1 \dut6[0].l4 (.in1 (x_out[0]), .in2 (n_out[0]), .sel (sel1), .o(m_out[0])); mux2_gate_2 \dut6[1].l4 (.in1 (x_out[1]), .in2 (n_out[1]), .sel (sel1), .o(m_out[1])); mux2_gate_3 \dut6[2].l4 (.in1 (x_out[2]), .in2 (n_out[2]), .sel (sel1), .o(m_out[2])); mux2_gate_4 \dut6[3].l4 (.in1 (x_out[3]), .in2 (n_out[3]), .sel (sel1), .o(m_out[3])); mux2_gate_5 \dut6[4].l4 (.in1 (x_out[4]), .in2 (n_out[4]), .sel (sel1), .o(m_out[4])); always @(adbar) if (adbar==1'b1) begin assign Z[0] = m_out[0]; assign Z[1] = m_out[1]; assign Z[2] = m_out[2]; assign Z[3] = X[5]; assign Z[4] = X[6]; assign Z[5] = X[7]; assign Z[6] = m_out[3]; assign Z[7] = m_out[4]; end else begin assign Z[0] = m_out[0]; assign Z[1] = m_out[1]; assign Z[2] = m_out[2]; assign Z[3] = X[3]; assign Z[4] = X[4]; assign Z[5] = X[5]; assign Z[6] = m_out[3]; assign Z[7] = m_out[4]; end endmodule 1 Answer
In Verilog you can model combinational circuits using assign or always. You can't mix them together.
If you want to model using assign, you can replace your always-block with following construct:
assign Z = adbar ? {m_out[4:3], X[7:5], m_out[2:0]} : {m_out[4:3], X[5:3], m_out[2:0]}; If you want to model using always, remove assign keyword from assignments and change Z output type from wire to reg.
