I know in HDL one can concatenate with c<={a,b};
but how is it represented in logic gates? signal concatenation keeps the order of the bits, so if i want to represent 2 one bit signals being concatenated into a one 2 bit signal and run that wire to another module, what is the logic block representation of the concatenation process?
I've already googled this question and searched, have not been able to find what I am looking for
c<={a,b};
2 Answers
You asked for a 'logic diagram' which is just two sets of wires combined into a third set of wires:
As dave_59 pointed out the result is a "unidirectional alias in that you can only read from c." I have tried to capture that feature in the diagram by using arrows on the wires.
Note that the concatenation operation does not add any logic and thus it does not cause any extra delay in the signals.
There is no hardware logic that represents concatenation—it simply creates an alias. (i.e. the MSB of c maps to the MSB of a, and so on).
BTW, using an assignment with a concatenation creates a unidirectional alias in that you can only read from c. SystemVerilog has a few other constructs to make bi-directional aliases, like the let and alias construct.
