when ever I compile this code, I get the following errors.
module mv2_generate ( input [127:0] c_array [1:0], input [127:0] p_array [1:0], input [127:0] p1_array [1:0], output reg [15:0] min_mv ); //genvar index; integer a, b, index, m; //genvar m; // a= (m*7)+m+7; // b= (m*7)+m; reg [7:0] read_dataC; //registers for C,P,P' reg [7:0] read_dataP; reg [7:0] read_dataP1; reg [15:0] out_pe0; reg pe0_en; pe PE0(.a(read_dataC),.b(read_dataP),.en(pe0_en),.pe_out(out_pe0)); always @* begin //generate for (index=0; index<2; index=index+1) begin // assign n=n+1; // a=7; // b=0; for (m=0; m<16; m=m+1) begin if(index<2) begin if (m>=0) begin read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m]; read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m]; // read_dataC = c_array [index] [a:b]; // read_dataP = p_array [index] [a:b]; #50; $display("pe out: %d",out_pe0); //pe PE0(read_dataC, read_dataP, out_pe0); end // a= a+8; // b= b+8; end end end end //endgenerate //assign min_mv= out_pe0; endmodule // module pe(input [7:0] a, input [7:0] b, input en, output reg [7:0] pe_out); //reg [15:0] acc_temp = acc; always @* begin //$display("End of Sim: %d", en); if(en) begin if (a<b) begin assign pe_out = b - a; end else if (a==b) begin assign pe_out = 8'd0; end else begin assign pe_out = a - b; end //acc_temp = acc_temp + pe_out; //acc = acc_temp; //$display("End of Sim: %d", acc); end else begin pe_out = 8'd0; end end endmodule The errors
ncverilog(64): 15.20-s029: (c) Copyright 1995-2017 Cadence Design Systems, Inc. file: mv2test.v read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m]; | ncvlog: *E,NOTPAR (mv2test.v,38|42): Illegal operand for constant expression [4(IEEE)]. read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m]; | ncvlog: *E,NOTPAR (mv2test.v,38|47): Illegal operand for constant expression [4(IEEE)]. read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m]; | ncvlog: *E,NOTPAR (mv2test.v,38|52): Illegal operand for constant expression [4(IEEE)]. read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m]; | ncvlog: *E,NOTPAR (mv2test.v,38|57): Illegal operand for constant expression [4(IEEE)]. read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m]; | ncvlog: *E,NOTPAR (mv2test.v,39|42): Illegal operand for constant expression [4(IEEE)]. read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m]; | ncvlog: *E,NOTPAR (mv2test.v,39|47): Illegal operand for constant expression [4(IEEE)]. read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m]; | ncvlog: *E,NOTPAR (mv2test.v,39|52): Illegal operand for constant expression [4(IEEE)]. read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m]; | ncvlog: *E,NOTPAR (mv2test.v,39|57): Illegal operand for constant expression [4(IEEE)]. module worklib.mv2_generate:v errors: 8, warnings: 0 module pe(input [7:0] a, input [7:0] b, input en, output reg [7:0] pe_out); | ncvlog: *W,RECOME (mv2test.v,83|8): recompiling design unit worklib.pe:v. First compiled from line 59 of mv2test.v. ncverilog: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1). 1 Answer
This is illegal in Verilog (and SystemVerilog):
c_array [index] [(m*7)+m+7:(m*7)+m]; Specifically, you cannot have a variable on the right hand side of a : in a part select. Instead you need to write either this:
c_array [index] [(m*7)+m+7 -: 8]; or this:
c_array [index] [(m*7)+m +: 8]; The value on the left hand side of the -: and +: operators is the starting index. The number on the right hand side is the width. This must be constant. Hence, your error. The -: operator counts down from the starting index; the +: operator counts up. The direction of the original array declaration does not matter: you can use either operator irrespective of the direction of the array.
