Is there a way to know in my testbench top about the current phase of the UVM hierarchy?. Since testbench top is a static module and UVM hierarchy is made of classes which are dynamic.
In my testbench top, I am directly driving few ports which is outside of UVM hierarchy. I need to stop driving these ports say after the shutdown phase. I can do it using uvm_config_db passing a phase from sequence but I don't want to create dependencies. I know it defeats the purpose of using UVM and reusability but just asking if I can do that?.
module top() initial begin drive_ports(); end virtual task drive_ports() //I need to keep driving these ports till shutdown_phase if (!uvm_tb_hierarchy.phase == shutdown_phase) //?? How to get phase?? dut.port = 8'hff dut.en = 1; endtask initial begin run_test() end endmodule 2 Answers
You can try this to get the current phase.
uvm_root top; uvm_phase curr_phase. uvm_coreservice_t cs = uvm_coreservice_t::get(); top = cs.get_root(); curr_phase = top.m_current_phase; Thanks, I tried the below code and it works. It seems each phase can be accessed at testbench top using "uvm_top.m_current_phase" provided you import uvm_pkg at testbench top. Since build_phase() starts at time 0, accessing this variable using initial_begin in testbench top was resulting in runtime error. So added wait statement in top TB and it works.
module top(); import uvm_pkg::*; int shutdown; initial begin wait (uvm_top != null); while (1) begin @(uvm_top.m_current_phase); if (uvm_top.m_current_phase != null) begin case (uvm_top.m_current_phase.get_name()) "pre_shutdown": shutdown = 1; endcase end end end endmodule 
