I am in the process of writing some Verilog modules for an FPGA design. I looked around the internet to find out how I best parametrize my modules. I see two different methods occurring often. I included an example hereunder of the two different methodologies. Which of these methods is the best way to parametrize modules? What is the difference? Is it vendor-dependent (Altera vs Xilinx)?
The first method: Module definition:
module busSlave #(parameter DATA_WIDTH = 1) ( input [DATA_WIDTH-1:0] bus_data, input bus_wr, ... ); endmodule Module instantiation:
module top; //DATA_WIDTH is 32 in this instance busSlave #(.DATA_WIDTH(32)) slave32( .bus_data(data_0), .bus_wr(wr_0), ... ); //DATA_WIDTH is 64 in this instance busSlave #(.DATA_WIDTH(64)) slave64( .bus_data(data_1), .bus_wr(wr_1), ... ); endmodule The second method: Module definition:
module busSlave( parameter DATA_WIDTH = 1; input [DATA_WIDTH-1:0] bus_data, input bus_wr, ... ); endmodule Module instantiation:
module top; //DATA_WIDTH is 32 in this instance busSlave slave32( .bus_data(data_0), .bus_wr(wr_0), ... ); defparam slave32.DATA_WIDTH = 32; //DATA_WIDTH is 64 in this instance busSlave slave64( .bus_data(data_1), .bus_wr(wr_1), ... ); defparam slave64.DATA_WIDTH = 64; endmodule 1 Answer
The defparam statement is scheduled for deprecation. The IEEE Std 1800-2012, Annex C (Deprecation), section "C.4.1 Defparam statements" states:
users are strongly encouraged to migrate their code to use one of the alternate methods of parameter redefinition.
Many features of Verilog are vendor-dependent.
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